PIR Sensor Interface
(16 Pins)

LS6506R-S, LS6506R, LS6507R-S, LS6507R

Category: PIR Motion Detection

Status: In Production

Stock Availability: DIP, SOIC

All of our Standard Products are RoHS Compliant

For pricing and availability you may contact us, or request a quote. Most of our standard parts are available for purchase on Digi-Key, and through our Distributors.

Features:

• LS6506R drives Latching Relay
• LS6507R drives Triac
• Same common features as the other PIR Sensor Interface except for the Dual Pulse Mode.
• Sensitivity adjustment
• Pushbutton for Manual-ON / Off control
• Ambient light override adjustment
• Selectable time-out adjustments
• 3 Operating Modes
  1. Manual On or Auto On / (Manual Off and Delayed Auto On or
  2. (Manual Off and Manual On) or Auto Off Manual On / Manual Off or Auto Off
  3. Manual On or Auto On / Manual Off or Auto Off
• Applications include Ceiling or Wall-Mounted Occupancy Sensors for control of florescent lights, electronic and magnetic ballasts, motors (LS6506R), incandescent lamps (LS6506R, LS6507R)
• Concurrent pulse mode

Description:

The LS6506R is a CMOS integrated circuit designed for room occupancy detection and can be used for switching power on to all types of AC loads. The circuit drives a two-coil latching relay. When the latching relay is engaged, full AC power is connected to the load. The LS6506R draws its power from the AC hot line and the house-ground connection that is located in a standard wall box. The maximum current draw from the ground line is 500µA RMS. The LS6507R draws its power from the AC HOT and AC NEUTRAL lines. All timing is generated from the AC input. The circuit contains a two stage PIR amplifier. The sensitivity can be adjusted by replacing R5 in Figure 2 with a potentiometer. Upon power up all inputs are disabled for a period of 56 seconds (60Hz operation) or 67 seconds (50Hz operation) in order for the PIR amplifier to reach its quiescent operating state. The circuit contains two operating modes. Refer to the datasheet for State Diagrams.

Ordering Info

Code
Package
Notes

P/N

RoHS Compliant Standard plastic DIP

1, 2, 3

P/N – S

RoHS Compliant Standard SOIC

1, 2, 3, 4

P/N – SW

RoHS Compliant Widebody SOIC option

1, 2, 3, 4

P/N – S14

RoHS Compliant 14-pin SOIC version of 8-pin part

1, 2, 3, 4

P/N – TS

RoHS Compliant TSSOP

1, 2, 3, 4

P/N – TS24

RoHS Compliant 24-pin TSSOP version of 20-pin part

1, 2, 3, 4

Example: LSxxxx-TS = the LSxxxx in the RoHS Compliant TSSOP package-type

Note 1: See Table for package body widths

Note 2: Package outline drawings conform to JEDEC standards

Note 3: Packages shipped in anti-static tubes

Note 4: Tape and Reel option available. Contact factory for details

ADDITIONAL ORDERING OPTIONS:

Probed Wafers (P/N-PW), Waffle Packed Die (P/N-WP)

Package Body Widths
# of Pins
P/N, -C, -CM
-S
-SW
-TS

8

300

150

14

300

150

173

16

300

150

300

18

300

300

20

300

300

173

24

600

300

173

28

600

300

173

38

173

40

600

44

240

LSI/CSI