LS7766SO-S, LS7766SO-TS, LS7766SO, LS7766SH-TS, LS7766DO-S, LS7766DO-TS, LS7766DO, LS7766DH-TS

The LS7766 consists of two identical modules of 32-bit programmable up/down counters (CNTR) with direct interface to incremental encoders. The modules can be configured to operate as quadrature-clock counters or non-quadrature up/down counters. In both quadrature and non-quadrature modes, the modules can be further configured into free-running, non-recycle, modulo-n and range-limit count modes. The mode configuration is made via two 8-bit read/write addressable mode control registers, MCR0 and MCR1. Data can be written into a 32-bit input data register (IDR), organized in addressable Word segments using the 16-bit IO bus or in byte segments using the 8-bit IO bus. The IDR can be used to store target encoder positions and compared with the CNTR for generating marker flags when the CNTR reaches the target value. A 32-bit digital comparator is included for monitoring the equality of the CNTR to the IDR. Snapshots of the CNTR value can be stored in a read-addressable 32-bit output data register (ODR). The ODR can be read in Word segments or byte segments in accordance with the selected bus width. Data transfers among the registers and various register reset functions are performed by means of a write-addressable 8-bit transfer control register (TCR). A read-addressable 8-bit status register (STR), stores the count related status information such as CNTR overflow, underflow, count direction, etc.