LS7466-S, LS7466-TS

LS7466 is a monolithic CMOS 24-bit programmable counter. It consists of two identical functional modules to interface with X and Y axes encoders simultaneously. Each block consists of the following registers: MCR0, MCR1, IDR, ODR, CNTR, DSTR and SSTR. MCR0 and MCR1 controls the functional modes. Data written into IDR is used to set limits to the counter (CNTR) range in several ways. CNTR can be uploaded into ODR for instantaneous or future read. DSTR dynamically follows the counter status in terms of carry, borrow etc. The instantaneous state of the DSTR can be latched into SSTR for future inspection.

Each axis can independently be configured to operate in 8-bit, 16-bit or 24-bit modular structures forcing IDR, CNTR and ODR into that configuration. Programmable modes include: X1/X2/X4 bi-directional quadrature or non-quadrature. Either of these modes can further be combined with Free-Run, Non-Recycle, Mod-N and Range-Limit modes.

A common SPI module establishes the communication between a host uC and the X and Y axis functional modules for bidirectional data transfers. The SPI module consists of the standard 4-wire IO’s namely, SS/, SCK, MOSI and MISO. Only mode0 bus protocol is supported.

LS7466 functions in the slave mode only. Any communication between LS7466 and a host controller is initiated by the host controller by bringing the SS/ input low followed by an instruction byte serially transmitted on the MOSI bus line. The instruction byte consists of an OP_CODE field for functional instruction, an address field for axis selection and another address field for register selection. The instruction byte gets loaded into the Instruction Register (IR) and executed at the completion of a communication cycle. A communication cycle consists of 1 to 4 consecutive bytes initiated by a SS/ low transition and completed when the SS/ switches high.